Howdy, Stranger!

It looks like you're new here. If you want to get involved, click one of these buttons!


[VHDL PROBLEM] Won't concatenate

Hello guy's, I have a small problem with a concatenation in vhdl.
I will post the code :
[code]Router_Nr_West <= DATA_TO_BE_ROUTE_WEST_IN(15 downto 8) + X"01";
i_data_vest <= DATA_TO_BE_ROUTE_WEST_IN(31 downto 16) & Router_Nr_West & DATA_TO_BE_ROUTE_WEST_IN(7 downto 0);[/code]

where DATA_TO_BE_ROUTE_NORTH_IN : in std_logic_vector(31 downto 0);
signal Router_Nr_West : std_logic_vector(7 downto 0);

I worck with a NanoBoard NB2 and Altium Designer Winter 09 and I am stuck at the simulation because the i_data_vest will have a value without the
Router_Nr_West. I attached a photo to ilustrate.

Thank's in advance.
Sign In or Register to comment.