Can you help me please?
Say CPU wants to read data from main memory:
- at time T1 CPU signals the address of memory location it wants
to read data from
- at time T2 the control signal tells the type of access CPU wants
to establish ( read access )
- at time T3 RAM puts on data bus the data requested by CPU
- when CPU receives data, it removes the control and address signals
-that causes main memory to remove, at time T4, data signals from
1) How do you call the time period between T1 and T5 ( I assume memory
access time )?
2) How do you call time period between T2 and T3?
3) Shouldnt the speed of RAM be specified with how long the time
period between T2 and T3 is? I assume this cos time periods T1-T2
and T3-T4 dont depend on the speed of RAM.