Hello,

I have got a Spartan 3E Evaluation Board and I want to give out on the Outputpins of the DAC a Counter-Signal.

The following is my VHDL-Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Zaehler is											-- I/O of Zaehler
    Port ( 	clk : in  STD_LOGIC;	 
				reset : in  STD_LOGIC;					
				break : in  STD_LOGIC;
			  
				CS 	: out STD_LOGIC;
				SYNC 	: out STD_LOGIC;
				SCLK 	: out STD_LOGIC; 
			  
				dout : out  STD_LOGIC;

				SPI_SS_B 	: out STD_LOGIC;
				AMP_CS 		: out STD_LOGIC;
				AD_CONV 		: out STD_LOGIC;
				SF_CE0 		: out STD_LOGIC;
				FPGA_INIT_B : out STD_LOGIC);
				
end Zaehler;

architecture Behavioral of Zaehler is
	signal counter_intern 	: std_logic_vector(11 downto 0) := "000000000000";			-- only internal signals
	signal counter_out		: STD_LOGIC_VECTOR(11 downto 0);
	
	type state_type is (read, write);																-- Statemachine with 4 states
	signal state : state_type := read;																-- first state = read

	-- internal signals
	signal cnt 				: integer range 0 to 32 := 0;
	signal newclk 			: STD_LOGIC := '0';


begin

	-- drive the DAC clock pins
	SCLK 		<= newclk;
	SPI_SS_B <= '1';
	AMP_CS 	<= '1';
	AD_CONV 	<= '0';
	SF_CE0 	<= '1';
	FPGA_INIT_B <= '1';
	
	converter : process(CLK, reset)
		variable temp : integer;
	
	begin
	if(reset = '1') then
		counter_out <= "000000000000";
	elsif(rising_edge(CLK)) then
		case state is
			when read =>
				CS <= '1';
				SYNC <= '0';
				if(cnt < 8) then																		-- stay for 4 cycles in read-mode without doing anything. 
					cnt <= cnt + 1;
				else
					if counter_intern < 16 then									
							counter_intern <= counter_intern + 1;								-- increment counter_intern
					else 
						counter_intern <= "000000000000";										-- counteroverflow
					end if;
				end if;
			counter_out <= counter_intern;														-- commit internal counter to output


			when write =>
				CS <= '1';
				SYNC <= '0';
				if (cnt = 8 or cnt = 9) then														-- send Command '0011'
					cnt <= cnt + 1;
					dout <= '0';
					state <= write;
				elsif (cnt = 10 or cnt = 11) then												-- send Command '0011'
					cnt <= cnt + 1;
					dout <= '1';
					state <= write;
				elsif (cnt = 12 or cnt = 13 or cnt = 14 or cnt = 15) then				-- send Address to select the output channels
					cnt <= cnt + 1;
					dout <= '0';
					state <= write;
				elsif(cnt > 15 and cnt < 28) then												-- output: 12 Databits (MSB first)
					cnt <= cnt + 1;
					dout <= counter_out(27-cnt);
					state <= write;
				elsif(cnt > 27 and cnt < 32) then												-- output: 4 don't cares
					cnt <= cnt + 1;
					state <= write;
				else
					cnt <= 0;																			-- return to write mode
					state <= read;
				end if;
			end case;
		end if;
	end process converter;

end Behavioral;

The Implementation of this design can be done, but I can't find the desired output with my scope.
I don't know, what's false in my code.

I hope anyone can help my.
Best regards....