I am new to VHDL !
I was trying ALU in VHDL ...
I could design Logic Unit but not Arithemetic unit. So, I checked out on the internet and found this code. But I am not able to understand the architecture part !!! PLEASE HELP !
Thnx !
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AU_4bit is
Port( a, b : in std_logic_vector(3 downto 0); -- inputs
s : in std_logic; -- select
g : out std_logic_vector(3 downto 0); -- output
Cout : out std_logic := '0');
end AU_4bit;
architecture Behavioral of AU_4bit is
signal sum, prod: std_logic_vector(3 downto 0); -- product and sum
begin
sum <= conv_std_logic_vector(UNSIGNED(a) + UNSIGNED(b), 4);
prod <= conv_std_logic_vector(UNSIGNED(a(1 downto 0))*UNSIGNED(b(1 downto 0)), 4);
g <= sum
when (s='0')
else prod;
Cout <= '1'
when (((conv_integer(a) + conv_integer(b)) > 15) and s='0')
else '0';
end Behavioral;
