Hey guys,
I am developing an Alu with VHDL, which consists of 3 entries and one out signal. The ALU performs 8 operations and one of them is shift. Unfortunately i am not able to write the shift operation properly. This is what my code looks like at the moment:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity alu is

port (
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
s : in std_logic_vector(2 downto 0);
c : out std_logic_vector(7 downto 0)
);
end alu;

architecture five of alu is

signal one : std_logic_vector(7 downto 0);
signal three : std_logic_vector(7 downto 0);

begin

one <= "00000001";
three <= "00000011";

c <= "00000001" when s = "000" and (unsigned(a) > unsigned(b))else "00000000" when s = "000" and (unsigned(a) <= unsigned(b)) else
"00000001" when s = "001" and (unsigned(a) = unsigned(b)) else "00000000" when s = "001" and (unsigned(a) /= unsigned(b)) else std_logic_vector(signed(a) + signed(one)) when s = "010" else std_logic_vector(signed(a) + signed(b)) when s = "011" else
a and b when s = "100" else
a or b when s = "101" else
std_logic_vector(b sla unsigned(three)) when s = "110" else
std_logic_vector(unsigned(a) mod unsigned(b)) when s = "111" else
"--------";
end five;


Has anybody an Idea, how could i write the shift function to make it work this way and become a vector as output? I would be very very thankful!

Thanks a lot!

Barney