## Electronics development

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Digital Tachometer - VHDL Posted by tachometer on 25 Mar 2012 at 1:21 AM
Hi,

I have this project where I have to design a tachometer using VHDL. The thing is I m pretty new to the field of electronic projects and I m very new to VHDL.
The project asks me to count the Rotations/per Minute from a motor.
It has to be in the range 19-98 RPM, the measurement time is 1.1s, and the display resolution is 0.1 .

The good part is that I dont have to create a system to get this rotations, they are given to me thru a generator. I just have to count the pulses and display the result.
http://imageshack.us/photo/my-images/546/blockvk.jpg
So, I tought I'll use an AND gate with the signal from the general as one input and the clock divided so I'll obtain the period of 1.1s .
http://imageshack.us/photo/my-images/839/clockbg.jpg/

What I have to do next is when i press a button it will count the pulses for 1.1s and then display the result. [During counting the display will be OFF].

Sorry for the long post but the first problem resumes to this. How do i design a clock divider so I can get a period of 1.1s.
I have a basic clock divider code where i count the rising edges and then i change the state of clock. But how many edges i have to count?

```ENTITY CLKDIV IS
PORT(
CLK: IN STD_LOGIC;
CLKOUT: OUT STD_LOGIC
);
END CLKDIV;

ARCHITECTURE DIV OF CLKDIV IS
BEGIN
PROCESS (CLK)
VARIABLE COUNT: INTEGER RANGE 0 TO ????  :=0;
VARIABLE STATE: STD_LOGIC := '1';
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(COUNT=  )THEN
COUNT:=0;
STATE:= '1';
ELSE
COUNT := COUNT+1;
END IF;
IF(COUNT=)
STATE:= NOT STATE;
END IF;
END IF;
CLKOUT <= STATE;
END PROCESS;
END DIV;
```

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