Electronics development Forum RSS Feed

subtraction of negative number

Thu, 26 Jan 2012 13:35:33 -0800

Hi

i am trying ot subtract a negative number as follows:

use ieee.std_logic_numeric.all

constant a signed(16 downto 0):= '0' & x"8000";
constant b signed(16 downto 0):= '1' & x"0030";

signal c signed(16 downto 0);

c <= a - b;

c should be 32816 but i get 32720

please help

Many thanks

simple multiplier/devider

Sun, 22 Jan 2012 05:09:54 -0800

hello,
i need your help with the folowing code.

The circuit has two 8 bit integer inputs a and b and two integer outputs x and y when x=a*b and y=a/2.
The code must be concurrent.

Here is what i wrote:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;

package my_data_types is
type integer_input is array (7 downto 0) of integer range -8 to 8;
end my_data_types;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;

entity mul_dev is
port (a,b: in integer_input(7 downto 0);
x,y: out integer_input (7 downto 0));
end mul_dev;

architecture Behavioral of mul_dev is

begin

x<= (a*b);
y<= (a/2);
end Behavioral;

I'm using xillinx ise progect navigator to simulate and i get the following errors:
<integer_input> is not declared.
Entity <mul_dev> is not yet compiled.

It seems he won't accept the pre defined array, what coul be the problem?

10x!

simple multiplier/devider

Sun, 22 Jan 2012 04:53:49 -0800

Need help for VHDL DICE Program

Sat, 07 Jan 2012 21:34:34 -0800

Hi! I'd like to ask all the VHDL knowledgeable people out there for help regarding a problem I came upon in our book.

1. Using Xilinx ISE 7.1 (We use Windows XP you see) create a VHDL program that:

1. System is idle until a ROLL button is pressed.
2. While ROLL button is pressed, the system adds the sum of two dice counters (which pulse at different signals to randomize the answer).
2. If the sum is 2, 3 or 11, a WIN output is given.
3. If the sum is 7, a LOSE output is given.
4. If the sum is any other number, store it in memory. In the next roll, if the new sum = stored sum, win the round.
5. If none of these conditions are met, the system loops rolling the dice until you either WIN or LOSE.

I'm not sure how to implement it in VHDL just yet, but we are told to use Mealy or Moore FSM to simplify the program. Here's what I came up with: (see attachment)

Need help for VHDL DICE Program

Sat, 07 Jan 2012 21:32:43 -0800

DINKLE

Mon, 19 Dec 2011 21:49:52 -0800

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This post has been deleted.

Mon, 19 Dec 2011 21:46:56 -0800

This post has been deleted.

How read Sensor outputs using a MC9S08DZ60 microcontroller

Mon, 21 Nov 2011 07:46:08 -0800

Hi All,
I need to connect six Tekscan A401 force sensors to a multiplexer and then transmit the o/p of these sensors via RS 485 to be given to a MC9S08DZ60 microcontroller.
Don't know how to do it. Can anyone help me how to do it?

How read Sensor outputs using a MC9S08DZ60 microcontroller

Mon, 21 Nov 2011 07:42:56 -0800

code for vhdl

Thu, 17 Nov 2011 07:13:35 -0800

i need a vhdl code for 16 counter.

code for vhdl

Thu, 17 Nov 2011 07:11:44 -0800

i need a vhdl code for 16 counter.

Quartus is optimizing away too much of my code

Tue, 15 Nov 2011 04:34:11 -0800

I need some serious help on this code. I've been tweaking the code for hours and nothing helps. I have a small case statement waiting for a change on an integer signal called index_2. For some reason that integer signal isn't changing, so Quartus removes my case statement from synthesis. What is going wrong? Why does quartus not think that index_2 is used at all?

In the code below I use a module called clk_enabler. That just sends a pulse once every n clock cycles, where n is 5208 for this code.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity serial_display is
port(	
        clock           : in std_logic;
        four_byte_in    : in std_logic_vector(31 downto 0);	
        bit_out         : out std_logic
);
end entity serial_display;

----------------------------------------------------

architecture behv of serial_display is

component clk_enabler is
generic(
        period: natural
);
port(	
        clock:          in std_logic;
	clear_L:        in std_logic;
	enable:         out std_logic
);
end component clk_enabler;

        signal clk_en_sig_1     : std_logic := '0';
        signal current_byte     : std_logic_vector(9 downto 0) := "1000000000";
	
        signal index_1 : integer range 0 to 9 := 0;
        signal index_2 : integer range 0 to 3 := 0;

begin

        process(index_2,index_1)
        begin
        CASE index_2 is
                when 0 => current_byte(8 downto 1) <= four_byte_in(31 downto 24);
                when 1 => current_byte(8 downto 1) <= four_byte_in(23 downto 16);
                when 2 => current_byte(8 downto 1) <= four_byte_in(15 downto 8);
                when 3 => current_byte(8 downto 1) <= four_byte_in(7 downto 0);
        end case;
		
                current_byte <= '1' & current_byte(8 downto 1) & '0';
                bit_out <= current_byte(index_1);
        end process;
	
        process(clk_en_sig_1, clock)
        begin
                if rising_edge(clock) and clk_en_sig_1 = '1' then
                        if index_1 < 9 then
                                index_1 <= index_1 + 1;
                        else
                                index_1 <= 0;
				
                                if index_2 < 3 then
                                        index_2 <= index_2 + 1;
                                else
                                        index_2 <= 0;
                                end if;
				
                        end if;
                end if;
        end process;
							
enabler: clk_enabler generic map(period=>5208)
                     port map(clock=>clock, clear_L=>'1', enable=>clk_en_sig_1);
	
end behv;

ALU VHDL with shift operation

Mon, 14 Nov 2011 01:47:43 -0800

Hey guys,
I am developing an Alu with VHDL, which consists of 3 entries and one out signal. The ALU performs 8 operations and one of them is shift. Unfortunately i am not able to write the shift operation properly. This is what my code looks like at the moment:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity alu is

port (
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
s : in std_logic_vector(2 downto 0);
c : out std_logic_vector(7 downto 0)
);
end alu;

architecture five of alu is

signal one : std_logic_vector(7 downto 0);
signal three : std_logic_vector(7 downto 0);

begin

one <= "00000001";
three <= "00000011";

c <= "00000001" when s = "000" and (unsigned(a) > unsigned(b))else "00000000" when s = "000" and (unsigned(a) <= unsigned(b)) else
"00000001" when s = "001" and (unsigned(a) = unsigned(b)) else "00000000" when s = "001" and (unsigned(a) /= unsigned(b)) else std_logic_vector(signed(a) + signed(one)) when s = "010" else std_logic_vector(signed(a) + signed(b)) when s = "011" else
a and b when s = "100" else
a or b when s = "101" else
std_logic_vector(b sla unsigned(three)) when s = "110" else
std_logic_vector(unsigned(a) mod unsigned(b)) when s = "111" else
"--------";
end five;

Has anybody an Idea, how could i write the shift function to make it work this way and become a vector as output? I would be very very thankful!

Thanks a lot!

Barney

VHDL questions

Sun, 13 Nov 2011 21:14:34 -0800

Hello. I was wondering how do I import and use an entity I created in one VHD file in another VHD file? What folder do I have to place the file in and how do I reference in the file I need to use it in.

Also, every time I try to put a second entity in a single VHD file I get a weird "out of virtual memory" error.Either tha, or it tells me that STD_LOGIC is reference but not used in the second entity, but not for the first. I tried placing the entities in different order and it is always the second one that throws the error.

Any help would be much appreciated!

VHDL questions

Sun, 13 Nov 2011 20:56:55 -0800

Need help with a basic VHDL test bench.

Fri, 28 Oct 2011 01:49:56 -0800

I am currently working on a stopwatch in VHDL, and made a counter module. Now I need to make a test bench for this module, and I am simply lost.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity countermodule is
    Port ( reset : in  STD_LOGIC_VECTOR (1 downto 0);
           startstop : in  STD_LOGIC_VECTOR (1 downto 0);
           clk : in  STD_LOGIC;
           Qout1 : out  std_logic_vector (3 downto 0);
           Qout2 : out  std_logic_vector (3 downto 0);
           Qout3 : out  std_logic_vector (3 downto 0);
           Qout4 : out  std_logic_vector (3 downto 0));
end countermodule;

architecture Behavioral of countermodule is

component Counter1 is
    Port ( res1 : in  std_logic_vector (3 downto 0);
           en1 : in  STD_LOGIC_VECTOR (1 downto 0);
			  clk : in	std_logic;
           countout1 : out  std_logic_vector (3 downto 0));
end component;

component counter2 is
    Port ( res2 : in  std_logic_vector (3 downto 0);
           en2 : in  STD_LOGIC_VECTOR (1 downto 0);
           clk : in  STD_LOGIC;
           countout2 : out  std_logic_vector (3 downto 0));
end component;

component counter3 is
    Port ( res3 : in  std_logic_vector (3 downto 0);
           en3 : in  STD_LOGIC_VECTOR (1 downto 0);
           clk : in  STD_LOGIC;
           countout3 : out  std_logic_vector (3 downto 0));
end component;

component counter4 is
    Port ( res4 : in  std_logic_vector (3 downto 0);
           en4 : in  STD_LOGIC_VECTOR (1 downto 0);
           clk : in  STD_LOGIC;
           countout4 : out  std_logic_vector (3 downto 0));
end component;

component Counter is
    Port ( clk : in  STD_LOGIC;
			  en : in std_logic;
           countout : out  STD_LOGIC);
end component;
begin


end Behavioral;

This is the code for my counter module, help will be appreciated.

Best regards

Fupson

Need help with a basic VHDL test bench.

Fri, 28 Oct 2011 01:48:05 -0800

I am currently working on a stopwatch in VHDL, and made a counter module. Now I need to make a test bench for this module, and I am simply lost.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity countermodule is
    Port ( reset : in  STD_LOGIC_VECTOR (1 downto 0);
           startstop : in  STD_LOGIC_VECTOR (1 downto 0);
           clk : in  STD_LOGIC;
           Qout1 : out  std_logic_vector (3 downto 0);
           Qout2 : out  std_logic_vector (3 downto 0);
           Qout3 : out  std_logic_vector (3 downto 0);
           Qout4 : out  std_logic_vector (3 downto 0));
end countermodule;

architecture Behavioral of countermodule is

component Counter1 is
    Port ( res1 : in  std_logic_vector (3 downto 0);
           en1 : in  STD_LOGIC_VECTOR (1 downto 0);
			  clk : in	std_logic;
           countout1 : out  std_logic_vector (3 downto 0));
end component;

component counter2 is
    Port ( res2 : in  std_logic_vector (3 downto 0);
           en2 : in  STD_LOGIC_VECTOR (1 downto 0);
           clk : in  STD_LOGIC;
           countout2 : out  std_logic_vector (3 downto 0));
end component;

component counter3 is
    Port ( res3 : in  std_logic_vector (3 downto 0);
           en3 : in  STD_LOGIC_VECTOR (1 downto 0);
           clk : in  STD_LOGIC;
           countout3 : out  std_logic_vector (3 downto 0));
end component;

component counter4 is
    Port ( res4 : in  std_logic_vector (3 downto 0);
           en4 : in  STD_LOGIC_VECTOR (1 downto 0);
           clk : in  STD_LOGIC;
           countout4 : out  std_logic_vector (3 downto 0));
end component;

component Counter is
    Port ( clk : in  STD_LOGIC;
			  en : in std_logic;
           countout : out  STD_LOGIC);
end component;
begin


end Behavioral;

This is the code for my counter module, help will be appreciated.

Best regards

Fupson

Udviklingskonsulent | It optimering

Sun, 25 Sep 2011 23:58:09 -0800

Database consultant is the most complete free directory of webia. hjemmeside udvikling.

http://webia.dk/Udvikling/Sharepoint.aspx

Type mismatch error in vhdl

Sat, 03 Sep 2011 12:12:21 -0800

Greetings! This is my first thread.

I have a package that contains the following type:

type t_rgb_64x48 is array(0 to 47) of std_logic_vector(63 downto 0);

and is being used in my file.vhd file.

------------------------

file.vhd contains an entity that contains the type of the package mentioned earlier:

RData_in : in t_rgb_64x48;
ColumnAddress_Start : in integer;
ColumnAddress_End : in integer;
RowAddress_Start : in integer;
RowAddress_End : in integer;

It also contains a signal with its corresponding type:

type t_vgaram is array(0 to 479) of std_logic_vector(639 downto 0);
signal s_rstorage : t_vgaram;

------------------------

I need to access s_rstorage through the following statement:

s_rstorage(ColumnAddress_End downto ColumnAddress_Start)
      (RowAddress_End downto RowAddress_Start)
        <= RData_in(ColumnAddress_End downto
                      ColumnAddress_Start)
                  (RowAddress_End downto RowAddress_Start);

to store the value of RData_in to s_rstorage and making sure that they are of the same width in 2D.

The problem is this error:

Type of s_rstorage is incompatible with type of RData_in.

I know that they have different types as the cause of the error. But how do I fix this problem?

how do i get it done!

Sat, 09 Jul 2011 11:05:16 -0800

heIIo most respected egineers

I am trying to deveIop a wireIess moisture sensor transmitter and wireIess receiver. I do not know exactIy how to get started. what do I buy. How do I go about it. is it possibIe to do it in the first pIace...I wiII be gIad if someone have Ideas...

Thanks
esedear

HC4538 Monostable Multivibrator in VHDL?

Fri, 01 Jul 2011 07:39:49 -0800

Hello, I'm new to VHDL and trying to model the chip hc4538. As can be seen in the datasheet, the output's pulse length is determined by Tau once the Vref is reached. I'm not exactly sure how to account for that in VHDL since it uses external components. Is it actually necessary to account for that? I've attached my code thus far.

Attachment: multivib2.vhd (431 bytes | downloaded 77 times)

Open pictures through voice command.

Mon, 27 Jun 2011 08:43:35 -0800

Is there a way for the UART “TX” serial output pin on my VoiceGP module to tell my computer to display a picture. Is it possible to create such an interface or is there an existing piece of technology that has serial input and is able to send commands to the computer through USB? Do I have to go from serial to USB? Is the device programmable? Does a program exist which takes USB input and is able to display a certain picture? Can I use something like Visual Studio to get USB input and do a ShellExecute() to display a picture?

THANK YOU FOR HELPING ME.

Hardware: VoiceGP DK-T2SI
Software:
VoiceGP IDE
Sensory Quick Synthesis 5
Sensory Quick T2SI
Computer:
64-bit Dell using Windows 7 OS

[VHDL PROBLEM] Won't concatenate

Sat, 25 Jun 2011 08:15:05 -0800

Hello guy's, I have a small problem with a concatenation in vhdl.
I will post the code :

Router_Nr_West <= DATA_TO_BE_ROUTE_WEST_IN(15 downto 8) + X"01";
 i_data_vest <= DATA_TO_BE_ROUTE_WEST_IN(31 downto 16) & Router_Nr_West & DATA_TO_BE_ROUTE_WEST_IN(7 downto 0);

where DATA_TO_BE_ROUTE_NORTH_IN : in std_logic_vector(31 downto 0);
signal Router_Nr_West : std_logic_vector(7 downto 0);

I worck with a NanoBoard NB2 and Altium Designer Winter 09 and I am stuck at the simulation because the i_data_vest will have a value without the
Router_Nr_West. I attached a photo to ilustrate.

Thank's in advance.

Attachment: untitled.JPG (58104 bytes | downloaded 67 times)

urgent: Interfacing SD Card to Atmega16

Tue, 10 May 2011 01:28:05 -0800

Hi friends,

I am working on my final year project. I want to interface SD card to Atmega16 microcontroller using SPI protocol. I tried interfacing but it didnt work. I need your help. Its very urgent. Please guide me on how to interface SD card and how to read and write data. I want to write three values(data) to SD card and I want to read them and display on LEDs. Please help me with interfacing and code. Its really urgent.
Thanks a lot.

coding equation in VHDL for implementation on FPGA

Tue, 26 Apr 2011 06:57:33 -0800

HI !!
i need help to do the VHDL program of :
d(n)=(kpc+kic.Tpwm).esp(n)+INTcurrent(n-1)
with :
esp(n)=Iplatref(n)-Iplatmeas(n)
thank u a lot!

Attachment: equation.doc (36352 bytes | downloaded 50 times)