Dose the A20 line remains disabled when entering pmode or it's enabled when entering protected mode?

10x

: Dose the A20 line remains disabled when entering pmode or it's enabled when entering protected mode?
:
: 10x
:
The A20 line is controlled independantly of the CPU mode.
You control it via I/O port 60h and 64h. (keyboard ports)

There are also other methods of controlling A20, but the keyboard port is the most common.

-jeff!

: : Dose the A20 line remains disabled when entering pmode or it's enabled when entering protected mode?
: :
: : 10x
: :
: The A20 line is controlled independantly of the CPU mode.
: You control it via I/O port 60h and 64h. (keyboard ports)
:
: There are also other methods of controlling A20, but the keyboard port is the most common.
:
: -jeff!
:

And even if I'm in pmode I can't address more then 1MB if the A20 line is disabled ?

: And even if I'm in pmode I can't address more then 1MB if the A20 line is disabled ?

You can access the even-numbered megabytes with A20 off (0-1MB, 2-3MB, 4-5MB, etc.) and the odd megabytes will mirror the data in the megabyte before it (1-2MB will contain the same data as 0-1MB and any writes to either will be immediately reflected into the other).

So you can only access up to half of the computer's memory in pmode with A20 off.

: : And even if I'm in pmode I can't address more then 1MB if the A20 line is disabled ?
:
: You can access the even-numbered megabytes with A20 off (0-1MB, 2-3MB, 4-5MB, etc.) and the odd megabytes will mirror the data in the megabyte before it (1-2MB will contain the same data as 0-1MB and any writes to either will be immediately reflected into the other).
:
: So you can only access up to half of the computer's memory in pmode with A20 off.
:


10x for your answers.
One more question.In pmode if you do not reinitialize the PIC to point at other interupts numbers what will happen when the timer sends interupt signals and the interupts are enabled?

: One more question.In pmode if you do not reinitialize the PIC to point at other interupts numbers what will happen when the timer sends interupt signals and the interupts are enabled?

Intel reserved interrupt table entries 0-31 for exceptions but IBM used much of that range for their first x86-based computer. Leaving the PIC's mapped how they were programmed by the BIOS would have the PIT fire an IRQ and cause the CPU to execute the handler corresponding to entry 8, which is also an exception (double fault). So how are you going to tell if your routine was called as an exception or IRQ handler? I know there is a way by asking the PIC, and EMM386 uses it, but the simplest way is to avoid the situation and remap your IRQ handlers out of the way of the exception handlers.

: : : Dose the A20 line remains disabled when entering pmode or it's enabled when entering protected mode?
: : :
: : : 10x
: : :
: : The A20 line is controlled independantly of the CPU mode.
: : You control it via I/O port 60h and 64h. (keyboard ports)
: :
: : There are also other methods of controlling A20, but the keyboard port is the most common.
: :
: : -jeff!
: :
:
: And even if I'm in pmode I can't address more then 1MB if the A20 line is disabled ?
:
in order to use the tull amount of ram plugged in your computer we have to enable the address line.. as mentioned earlier enabling a line of the floppy controller can do this. setting the appropriate bit can change hte state of this line. this bit the second bit of at keyboard controller output setting this second bit