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VHDL Basics

"Basics of VHDL" blog provide information about VHDL language and syntax for design and Verification to the beginners. Note:- This series...
Posted on Thursday, January 28, 2010 at 8:42 PM

Chapter4.Data Objects, Types and Operators(Continued)


4.2:Data Types:-

Data type is an attribute which specify which type of data an object can hold. Data types which are frequently used in VHDL will be discussed here.

4.2.1 STD_LOGIC:-

STD_LOGIC holds any one of the following values

'0', -- force 0

'1', -- force 1

'w', -- weak unknown

'u', -- uninitialized

'z', -- impedance

'h', -- weak 1

'l', -- weak 0

'x' and -- force unknown

'-' -- don't care.

Example 4.1:- SIGNAL a : STD_LOGIC; a <= '0';

Example 4.2:- VARIABLE a : STD_LOGIC; a := '1';

4.2.2 STD_LOGIC_VECTOR:-

STD_LOGIC_VECTOR holds an one dimensional array values as same as std_logic

Example 4.3:- SIGNAL a : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; -- Here ":=" is used to initialize the signal value this is recommended only in test bench not for writing RTL code.

a <= "0010";-- for assigning the values "<=" is used.

4.2.3 INTEGER:-

Integer holds the value ranges from –2147483647 to +2147483647.

Example 4.4:- SIGNAL a : INTEGER RANGE 0 TO 50;

4.2.4 TYPE:-

TYPE is to define set of values and operation.

Example 4.5:- TYPE state IS (ST_Write,ST_Read,ST_write); SIGNAL bus_operation : state;

In the above example bus_operation signal will hold the any one of the "state" type defined by the user.

Example 4.6:- TYPE two_dimension IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR;

4.2.5 RECORD:-

RECORD used to collect different data types together.

Example: 4.7:-

TYPE grp_function IS

RECORD

address : STD_LOGIC_VECTOR(31 DOWNTO 0);

data : STD_LOGIC_VECTOR(31 DOWNTO 0);

bus_operation : state; -- state type is defined in example 4.5

END RECORD;

VARIABLE bus : grp_function;

In the example "bus" holds different data types.

Above data types are often used in coding. Few data types are not explained are ACCESS type, FILE type, SUBTYPE, ATTRIBUTES, SIGNED, UNSIGNED, STD_ULOGIC etc.,

4.3 Operators:-

Operators in an language is used to perform the logic and arithmetic operation.

Predefined VHDL Operators are

LOGICAL

ARITHMETIC

SHIFT

RELATIONAL

4.3.1 LOGICAL:-

Logical Operators are AND, OR, NAND, NOR, XOR, NOT, XNOR.

Example 4.7:- c <= NOT(a AND b XOR c);

4.3.2 ARITHMETIC:-

Arithmetic Operators are +, -, /, *, MOD, REM.

Example 4.8:- c <= (a + b - c)*a;

4.3.3 SHIFT:-

Shift Operators are SRL(Shift Right Logical), SLL(Shift Left Logical), SLA(Shift Left Arithmetic), SRA(Shift Right Arithmetic), ROL(ROtate Left logical), ROR(ROtate Right logical).

Example 4.9:- VARIABLE s_opr : STD_LOGIC_VECTOR(3 DOWNTO 0):= "1011";

s_opr SLL 2; -- results in "1100"

s_opr SLA 2; -- results in "1111"

s_opr ROL 2; -- results in "1110"

4.3.4 RELATIONAL:-

Relational operators are =(equal to), /=(not equal to), <(less than), >(greater than), <=(less than or equal to), >=(greater than equal to).

Note:- "<=" is used to assigned the value of a signal. If it is used as a <= b; in a concurrent statement. In sequential statements it will be used to compare two signals or variables, which we will discuss in upcoming chapter.
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