5.1:Introduction:-
VHDL is broadly classified into two types based on the execution of statements. They are
a) Concurrent statement
b) Sequential statement
This chapter will give an explanation about two types of statements and their categories. These statements are commonly used in synthesis.
5.2:Concurrent statement:-
Concurrent statements are executed parallely. Inside the architecture of VHDL program, all the statements are executed simultaneously i.e., all the statements are executed at the same time. They are concurrent. The order of the statements is not important. Few concurrent statements are
a) Boolean equation
b) when else
c) with select when
5.2.1:Boolean Equation:-
Boolean equation forms combinational logic and produce desired output for design. LHS variable is assigned with one or more variables connected with or without operators such as AND,OR,NOT,XOR,NOR,+,*,/,- etc to form Boolean equation.
Example 5.1:-
Refer example 4.7 and example 4.8
Note:- Boolean equation has to be outside process.
5.2.2:when else:-
when else statement gives the output based on the condition which it satisfies first. Priority goes on the order of appearance. It forms a priority encoder.
Example 5.2:-
-- xor operation in when else
c_o <= '0' when (a_i = b_i) else '1';
5.2.3:with select when:-
Target signal will be assigned as soon as the control signal is ready in "with select when" statement. It forms encoder logic after synthesis. Control signal will be placed between "WITH" and "SELECT" keyword. Target signal is followed by "SELECT" keyword.
Example 5.3:-
-- concatenation is done here else
-- simulation warning select signal has to be "static"
-- sel_s has to be declared between architecture and begin with two
-- bit vector.
sel_s <= (a_i & b_i);
-- sel_s is control signal
WITH (sel_s) SELECT
-- c_o target signal
c_o <= '0' WHEN "11",
'0' WHEN "00",
'1' WHEN OTHERS;
Apart from the above classification "PROCESS" is a concurrent statement. Statements inside PROCESS will execute when there is activity in the sensitivity list or by wait statements inside PROCESS.
5.3:Sequential statement:-
Sequential statements are executed one by one. Inside "PROCESS" of the VHDL program all the statements are executed one by one. If a signal is assigned twice in a same PROCESS the statement which is assigned in last statement will be considered to assign value for the signal. The order of the statement is very important. Below sequential statements commonly used in synthesis
a) Case
b) if else
5.3.1:case:-
In case statements only one branch is executed at a time. Case statements form a multiplexer after synthesis. It is similar to "WITH SELECT WHEN" concurrent statement.
Example 5.4:-
-- concatenation is done here else
-- simulation warning select signal has to be "static"
-- sel_s has to be declared between architecture and begin with two bit vector.
-- process deceleration with sensitivity
PROCESS (a_i,b_i,sel_s)
BEGIN
-- concatenation of two bits
sel_s <= (a_i & b_i);
--sel_s is control signal
CASE (sel_s) IS
-- "|" is not or operator
-- it indicates that if sel_s is either "00" or "11" then executes
WHEN "00" | "11" =>
c_o <= '0';
-- all the other cases like "01", "10" condition
WHEN OTHERS =>
c_o <= '1';
END CASE;
END PROCESS;
5.3.2:if else:-
Only "if" statement is possible but it forms latch. Nested If else statement is also possible in which one or more conditions are satisfied then it executes the first satisfied condition only. It forms priority encoder. It is similar to "when else" concurrent statement.
Example 5.5:-
-- whenever there is a change in a_i or b_i
-- then the statements will be executed
PROCESS (a_i,b_i)
BEGIN
-- both inputs are equal then target signal is assigned to 0
IF (a_i = b_i) THEN
c_o <= '0';
-- both inputs are not equal then target signal is assigned to 1
ELSE
c_o <= '1';
END IF;
END PROCESS;
NOTE:-
Other sequential constructs which are synthesizable is FOR LOOP and some tools support LOOP, WHILE also for synthesis. But these LOOP constructs are not advisable for synthesis. FOR LOOP completes the execution in one time unit i.e. within one clock cycle.
