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"Power Everywhere" Gains Momentum
What was the motivation behind making HCL Technologies the first external product design center for IBM? What IBM technologies will HCL have access to, and how will it use them? What's in it for IBM and both current and potential customers? Raj Narayanaswamy, marketing manager for HCL Technologies, <explains.
A developer's guide to the PowerPC architecture
PowerPC processors are found in everything from supercomputers
to game consoles and from servers to cell phones -- and they
all share a common architecture. This introduction to the
PowerPC application-level programming model will give you an
overview of the instruction set, important registers, and other
details necessary for developing reliable, high performing
PowerPC applications and maintaining code compatibility among
processors.
A History of Chipmaking at IBM
In the last decade alone, IBM scientists have announced one semiconductor breakthrough after another: copper technology, silicon-on-insulator, silicon germanium, strained silicon, and low-k dielectrics. All of these technologies came out of IBM's fertile in-house research community. This prowess in modern chipmaking know-how didn't come out of a vacuum -- rather, it came out of the hermetically-sealed clean rooms of the most advanced R & D department in the semiconductor industry.
AltiVec to improve performance on G4 and G5 PowerPC Chips
Motorola AltiVec can dramatically improve the performance of
many tasks, even tasks that you might initially think are too
linear to get much advantage from parallelizing. This article
looks at some real-world code that processors might spend a
serious amount of time running, and shows how to tweak it to
get extra performance.
Avoid the Cost of New Hardware through Emulation
This article introduces PowerPC emulation and cross-compiling for developers without access to real hardware. It is intended for developers familiar with computer architecture who own an x86-based workstation but are interested in experimenting with PowerPC.
Big iron lessons: FPU architecture, now and then
Floating point provides a convenient, approximate representation of real numbers that can greatly simplify scientific and engineering algorithms. This article gives an overview of two floating point formats used in the z990 architecture and discusses key FPU issues that system architects should consider in new designs.
Branching Registers with the PowerPC Processor
In Part 1 of this series you saw how programs on the POWER5 processor work using the 64-bit PowerPC instruction set, then in Part 2 you learned how the PowerPC instruction set addresses memory, and how to do position-independent code. In this article, you learn how to use the very powerful condition and branch instructions available in the PowerPC instruction set.
Build a minimal embedded Web interface
This installment shows you how to use small-footprint, highly portable, Free Software tools to Web-enable your unmanned submarine, in anticipation of browsing its onboard photo library from an underground lair in the next episode.
Call Functions with PowerPC ABI for 64-bit ELF
This article discusses the PowerPC ABI for 64-bit ELF (UNIX-like) systems and how to write and call functions using it. This is helpful for writing 64-bit programs for the POWER5 and other PowerPC-based processors more effectively, whether you program in assembly language or not.
Cell BE Programming and Extensions to Linux
Join us while we explore the details of Cell Broadband Engine (Cell BE) programming. This Tech briefing provides a comprehensive technical overview of the Cell BE architecture, programming models, and software development environment. You will learn all about Cell BE standards like the application binary interface specifications, SPE C/C++ language extensions, SPE assembly language specification, system-level simulator, Cell BE simulator debugging environment, and Cell BE extensions to Linux.
Cell Broadband Engine Processor DMA Engines
Part 1 in this series described the internals of the Cell Broadband Engine architecture and the main components that provide the on-chip DMA capabilities between the PPE and the SPEs. While the previous article covered DMA initiated by the PPE's Memory Flow Controller (MFC), this article delves deeper into the other half of the on-chip DMA transactions, covering the Cell BE processor's SPE DMA architecture, channels, and DMAs from the SPE's perspective.
Clean Up Cell/B.E. App Bugs
Cell/B.E. is the result of collaboration among IBM, Sony, and Toshiba to design a high-performance and power-efficient processor. Allinea Software's Distributed Debugging Tool (DDT) provides an easy-to-use, capable debugger for Cell/B.E. applications, including multiple threads within a single Cell/B.E. processor or clusters of them.
Configuring a Secondary Processor to Handle Tasks
Lewin Edwards demonstrates how to talk to an AVR(R)-based real-time module from a 32-bit Linux host. The design goal is to offload simple real-time tasks to the peripheral microcontroller. The other parts of this series can be found here.
Container Virtualization for Cell/B.E. and Linux Part 2
Learn about efficient virtualization for the Cell/B.E. processor regarding hardware resources called container virtualization, and the open source software OpenVZ Linux project. This second article details the implementation of dedicated virtualization and partitioning described in Part 1.
CPI Analysis on POWER5
Cycles per instruction (CPI) is the measurement for analyzing the performance of a workload. This article begins a short series on workload performance analysis on Power Architecture systems. Part 1 introduces the CPU feature set and a variety of useful tools for collecting data.
Denali Verification and Testing for Power Architecture
Sanjay Srivastava, president and CEO of Denali Software, Inc., talks about his ten-year-old company's entry into the hardware verification arena, its partnership with IBM to develop verification and compliance software for designs using the CoreConnect on-chip bus, and how Denali works within Power.org to develop open standards.
Develop Applications on Linux on POWER
Learn how to develop and deploy your applications on Linux on IBM System p and System I POWER-based servers. This article discusses the similarities and differences that you need to be aware of for the Linux on POWER systems.
Essential Tools and Techniques for Debugging Cell BE Systems
Programmers face several new challenges in developing applications for the Cell Broadband Engine (Cell BE) processor. With nine cores, multiple ISAs, and non-coherent memory, the design of the Cell BE processor is more complex than traditional architectures, and can be quite intimidating. However, this complexity can be overcome with the tools Cell BE SDK provides to aid in debugging. This article describes how to use new versions of the GNU Debugger (GDB) to diagnose problems in both PPU and SPU programs.
Experts Discuss SLOF Development and Usage
Slimline Open Firmware (SLOF) provides a largely machine-independent BIOS, illustrating what is needed to initialize and boot Linux. Three of the original SLOF developers discuss the development and usage of SLOF, initialization/boot source code for the PowerPC based on the Open Firmware standard.
Fundamentals of POWER5 Assembly Language
The POWER5 processor is a 64-bit workhorse used in a variety of settings. Part 1 of this Assembly language for Power Architecture series is an introduction to assembly language concepts and the PowerPC instruction set. The series as a whole will introduce assembly language in general, specifically language programming for the POWER5.
Get Hands-On Experience Programming Blue Gene
The integrated Cell BE SDK supersedes all previous versions, and now contains Support for Linux kernel 2.6.16, GNU GCC 4.0.2, and binutils 2.16.1, Support for PowerPC 64-bit hardware, NUMA, XL C compiler now supports C++, and a greatly enhanced install experience. Download the new Cell Broadband Engine and gain hands-on experience programming Blue Gene.
Implications for Power Architecture
Major electronics companies have come together to form a new standards body focused on Power Architecture technology. Power.org will create and promote a family of standards, reference designs, and more. Here's a developer's-eye view of the future and implications for Power Architecture standardization.
Initializing Memory Efficiently on Power Architecture Platforms
Learn to efficiently initialize memory on Power Architecture systems. Software Developer Carlos Cavanna compares simple loops clearing one bit at a time to more elaborate algorithms, including the dcbz instruction to zero whole cache lines at a time. The article concludes with some rough performance numbers to help you tune your own applications.
Introducing the CPI Breakdown Model
Make substantial improvements in performance analysis with a CPI analysis model built on the tools introduced in Part 1. Learn ways to analyze the specific performance counter data produced by profiling runs to obtain statistics for events which the CPU cannot directly report on.
Java Environments for Linux on POWER Architecture
In this article, Linux on POWER refers to the coupling of multiple distributions of the Linux operating system with POWER and PowerPC (abbreviated as PPC) processors, which are IBM's family of general-purpose and embedded processors tied together under the collective term Power Architecture. This article provides a brief overview of the currently available Java Development Kits (JDKs) and Java Runtime Environments (JREs)for Linux on POWER.
Kuro Box Linux up close
This installment of "Migrating from x86 to PowerPC" moves from the abstract to the concrete, looking into implementation details of the Kuro Box. The article gets into actual implementation specifics for the Kuro Box platform.
Launch the New Cell BE Software Development Kit
This article gives a brief overview of what is available to help you get started on your own Cell BE development projects. The latest release of the Cell Broadband Engine (Cell BE) Software Development Kit (SDK) introduces some new features, improves the installation procedure, and provides expanded documentation.
Load Linux on the Mac mini
The Mac mini is an ideal low-cost, high-performance PowerPC development platform for numerous applications. Learn how to install and configure Linux on the mini. Future articles will add the software required to make it into a stand-alone multimedia appliance.
Looking at Real Time for Linux, PowerPC, and Cell
A great philosopher once said, "Time is an illusion, lunchtime doubly so." What about real time? Specifically, what about Linux and real time? Paul McKenney of IBM discusses processors, computer history, time slices, games, physics, and Linux.
Making the transition to 64 bits
As 64-bit PowerPC processors become more widely available, it
becomes desirable to make applications run in the 64-bit
computation mode, providing access to larger address space and
faster 64-bit arithmetic. This excerpt from a longer Technical
Library article covers some of the issues faced when porting
existing 32-bit code to the new computing model -- or when
embarking on new 64-bit development.
Maximize Cell BE with 25 Application Performance Tips
Unlike on conventional processors, you can achieve near theoretical-maximum performance for real applications on the Cell Broadband Engine (Cell BE) processor. Get to know Cell BE processor’s architectural characteristics better with these 25 tips to optimal application performance. With these tips, now you can be on you way to theoretical-maximum performance.
Measure Time in Linux with Time Base
Use the PA technology's Time Base register to measure time at the nanosecond level in Linux on PowerPC and Cell BE microprocessors. Applications where this is useful include timestamping transactions (typically encrypted or digitally signed single-use messages), profiling code, and implementing small, precise software delays.
Migrate Win32 C/C++ application to Linux on POWER Part 2
This of article helps you migrate your Win32 C/C++ applications to Linux on POWER. Win32 C/C++ Apps to Linux Part-2 illustrates how to map Win32 to Linux with respect to mutex application program interfaces (APIs).
Migrating from x86 to PowerPC
This series on embedded development shows you how to migrate a project prototype from x86 to PowerPC. This initial installment explains the realities and rationale of the project: it introduces the robotic submarines that were the start of the project (and where they came from), and describes the Linux/GCC development environment and the bare-bones Kuro Box PowerPC development board.
Migrating from x86 to PowerPC, Part 1: Robots and networked appliances on a shoestring
This series on embedded development shows you how to migrate a project prototype from x86 to PowerPC. This initial installment explains the realities and rationale of the project: it introduces the robotic submarines that were the start of the project (and where they came from), and describes the Linux/GCC development environment and the bare-bones Kuro Box PowerPC development board.
Migrating from x86 to PowerPC, Part 2: Anatomy of the Linux boot process
This installment of "Migrating from x86 to PowerPC" discusses detailed similarities and differences between booting Linux on an x86-based platform (typically a PC-compatible SBC) and a custom embedded platform based around PowerPC, ARM, and others. It discusses suggested hardware and software designs and highlights the tradeoffs of each. It also describes important design pitfalls and best practices.
Migrating from x86 to PowerPC, Part 4: Build a minimal embedded Web interface
This installment shows you how to use small-footprint, highly portable, Free Software tools to Web-enable your unmanned submarine, in anticipation of browsing its onboard photo library from an underground lair in the next episode.
Migrating from x86 to PowerPC, Part 8: Add stepper motors to the vehicle control module
Lewin Edwards reviews the I/O expansion possibilities for the slave microcontroller on the robot submarine. The Inter-IC Communication (I2C) bus provides a simple and compatible way to expand the submarine's I/O options and connect it to a number of stepper motors.
Multifunction multimedia machine, Part 1: Load Linux on the Mac mini
The Mac mini is an ideal low-cost, high-performance PowerPC development platform for numerous applications. Learn how to install and configure Linux on the mini. Future articles will add the software required to make it into a stand-alone multimedia appliance.
New & Improved 750GX Datasheet
See the newly updated 750GX datasheet, including more on reduced-lead packaging and better package drawings. Learn about the required pullup resistors for the Marvell Discovery III PowerPC controller. And discover how to get a tip on the topic of your choice.
New Techniques Aid Chips' Energy Efficiency
IBM first introduced power-saving, frequency-shifting techniques in its PowerPC 750 line of processors. As process geometries have shrunk further, power dissipation has become even more of a challenge, and engineers have worked hard to improve power-saving technologies and maintain performance. This quick read gives insight on how these techniques have advanced in more recent chips.
Power Architecture’s New Identity
Michael E. Sullivan of IBM discusses how Power Architecture technology is being reborn under Power.org as a community-driven architecture and brand inspired by the open-source Linux model. Learn what motivated the changes, what they will mean for customers and partners, and what the new logo symbolizes.
POWER Expert: Regina Darmoni
This question and answer article features the IBM Program
Director of PowerPC licensing, Regina Darmoni. Regina has led
the PowerPC licensing effort from the concept stage to the
present and talks about general license terms and what's
available -- and what it's like to be the little guy.
Power.org at the One-Year Crossroads
As Power.org celebrates its first birthday, take a look at what happened in year one and what's ahead. MacLaren Harris interviews Marketing Programs Manager for Power.org Jesse Stein and discovers what is working and what needs work; how Power.org has grown and what has been achieved; and how individual developers can participate.
PowerPC Architecture Book, Version 2.02
This 3 volume set, Version 2.02, defines the instruction and registers used by application programs, the storage models, privileged facilities, and related instructions for the POWER5 processor family.
PowerPC Assembly
Assembly language is not widely known among the programming community these days, and PowerPC assembly is even more exotic. This article presents an overview of assembly language from a PowerPC perspective and contrasts examples for three architectures: ia32, ppc, and ppc64.
PowerPC Compiler Writer's Guide
This book describes, mainly by coding examples, the code patterns that perform well on PowerPC processors. The book will be particularly helpful to compiler developers and application-code specialists who are already familiar with optimizing compiler technology and are looking for ways to exploit the PowerPC architecture. It will also be helpful to application programmers who need to understand and tune the output of PowerPC compilers and to faculty members and graduate students specializing in the study of compilers.
Programming the cache on the PowerPC
While many programs can obtain acceptable performance by simply
letting the processor manage its own caching, programs with
special requirements may obtain dramatically improved
performance by giving the processor explicit instructions and
manipulating the cache directly. More typically, boot firmware
may need to flush and enable the cache.
The Cell BE Processor Security Architecture
As computers and consumer electronics devices become more connected, platform security becomes increasingly important for everyone from consumers to businesses. For consumers, privacy of data such as credit card numbers and social security numbers have always been of concern, but now new technologies such as voice-over-IP and personal video blogs bring new privacy concerns. The unrelenting evolution toward an even more open and connected computing infrastructure requires robust security to thrive. Learn how the Cell Broadband Engine processor's security architecture is uniquely suited for the challenges of this digital future.
The first Power Architecture Technical Briefing
This question and answer session features Stanley Kwong, the person in charge of worldwide technical briefings for IBM. Stan handles developerWorks briefings and is about to orchestrate the first-ever briefing on the Power Architecture-related dW event in the People's Republic of China.
The Gift of Technology Palm-Reading
Instead of making technology predictions for 2006, the Power Architecture challenge takes prognosticators to task, <a href=http://www.ibm.com/developerworks/power/library/pa-chipschall13/?ca=dgr-lnxwTechFortune>debunking some classic fortune-telling myths</a>, showing how much successful scrying and blindfolded dart-playing have in common.
The Microsoft Xbox 360 PowerPC CPU Story
Read about the design, verification, and making of the 165-million-transistor Xbox 360: a first-pass-good processor with advanced debug and test features, designed to the exacting standards of a gaming platform, with high throughput, low latency, low cost and low power - and very tight deadlines.
The More Processors, the Better Your System
Achieve a level of high reliability in a microprocessor system by adding a second identical processor to a system to monitor and verify the system processor operation -- also known as the lockstep processor technique. This tip demonstrates the integrated lockstep facility (LSF) in the PowerPC 750GX processor.
The Power in Xilinx
Several years ago, the IBM and Xilinx relationship resulted in the "immersion" of the IBM PowerPC processor cores into the Xilinx family of Virtex-II FPGAs. The PowerPC architecture has seen successful adoption in high-performance embedded systems and runs much of the world's networking and communications infrastructure. By migrating that standard of success with the PowerPC core into programmable logic, Xilinx has successfully delivered the highest performance FPGA processing solution into existing and new markets.
Tips and Tricks for MacsBug
Helpful techniques for debugging your Mac OS software using the MacsBug assembly debugger for 68000 and PowerPC code. Some of this I learned while working as a "Debug Meister" for Apple's system software team.
Tuning Your CPC945 Memory Controller
Explore the register-level details of tuning the CPC945's double data rate 2 (DDR2) memory controller for specific hardware implementations. Author Neil Leeder introduces nifty self-calibrating hardware features of the CPC945 to help you learn how to operate reliably with different memory configurations.
Understanding 64-bit PowerPC architecture
Each of the leading microprocessor manufacturers has announced
the availability of one or more 64-bit desktop processors, but
differences exist in architectural design, fabrication,
support, and intended use of each processor. This article looks
at the critical issues in a few of IBM's 64-bit POWER designs,
covering 32-bit compatibility, power management, processor bus
design, and the manufacturing process.
Water-Cooled Microprocessors: The Next Big Thing in Chip Cooling
The future of processor cooling might be in a new water jet technique. A little spray of water on the backside of a processor might be the next big thing in chip cooling. Also, learn about how Robot/CHECKUP service tells your iSeries where it could be better automated, and a new partnership for IBM to build cluster of software and hardware design centers in Wales.
